Crossbar (crosspoint) switches for digital signal transmission in prior art have used as a switching element at each crosspoint such passive (signal nonregenerative) switching elements as metallic switches and gated diode switches. Where such switches are used for switching digital signals having the relatively high digital signal transmission rates of over about 50 to 100 megabits per second, clock recovery and reconstruction of signal become difficult if not impossible, because of signal deterioration caused by various parasitics of these passive switches. More specifically, the relatively long interconnecting wires, necessitated by the relatively large size of each such switching element, and the relatively high parasitics of series resistance and parallel capacitance, both of the interconnecting wires and of the switching elements themselves, result in both lumped and transmission line parasitics which produce undesirable delays and distortion in the digital signals propagating through the crossbar switch. Thus, unwanted delays in the propagation times and deteriorations of the waveforms of these signals result. In particular, the amplitudes of digital signal pulses are reduced and the pulse edges thereof become diffuse. Moreover, these delays are different for upward vs. downward going input signal pulse edges and for each signal vs. its complement (inverse), and in general are also different for different subscribers transmitting signals to a given subscriber at different times or for a given subscriber transmitting signals to various other subscribers at the same time. That is to say, these delays cause all sorts of signal skew, the term "skew" being used herein to include not only discrepancies and variations in delays and widths of each signal pulse as compared with its complement but also pulse width and amplitude distortion of a single signal pulse. Accordingly, clock (timing) recovery and reconstruction of the original signals after propagating through the crossbar switch become difficult if not impossible at the above-mentioned high data rates.
On the other hand, the use of active (regenerative) switching elements that are interconnected to form a multiplicity of cascaded stages of logic gates in a logic circuit arrangement has been suggested in a paper by M. Sunazawa et al. published in IEEE Journal of solid-State Circuits, Vol. SC-10, pages 117-122 (1975) entitled "Low Power CML IC Crosspoint Switch Matrix for space Division Digital Switching Networks." In that circuit, in order to avoid skew, bipolar transistors were used as the switching elements in emitter coupled logic (ECL) in which the switching delay times of each of the cascaded logic gates formed by the transistors were much less than the pulse widths of the digital signals propagating therethrough. For data rates in the range of 100 to 300 megabits per second, for example--i.e., pulse widths in the range of 10 to 3 nanoseconds, a total signal skew of as little as about 2 to 0.6 nanoseconds is required to recover the clock signal. That is, the allowed variation in pulse width is only about one-fifth the pulse width or less--after propagation of the signal through the multiplicity of cascaded stages of gates. To achieve this objective using conventional circuit designs, a delay per logic gate of about 0.3 to 0.1 nanoseconds is desirable--i.e., a delay per gate of about one-sixth the total skew in such an arrangement. However, although bipolar transistor technology can satisfy these requirements in theory, nevertheless the size of bipolar logic gates is so large (because of the need for isolating individual bipolar transistors), and the standby power and heat dissipation problems are so great, that in practice it is unduly complex, difficult (if at all possible), and costly to manufacture a crossbar switching arrangement as large as 64 input .times.17 output in bipolar technology, especially in a single silicon semiconductor chip. On the other hand, CMOS technology does not suffer from the large gate size and power dissipation problem of bipolar technology but suffers from a longer gate delay per logic gate, in the range of about 0.6 to 1.2 nanoseconds. Therefore, CMOS technology would be a good substitute for bipolar technology in a crossbar switching arrangement if a novel design strategy could be found to enable a CMOS crossbar switching arrangement to handle data rates as high as 100 megabits per second or more in a 64 .times.17 crossbar switch, for example.
In CMOS (complementary MOS) technology, as known in the art, each CMOS logic gate comprises one or more p-channel MOS field effect transistors (PFETs), located in a PMOS portion of the gate interconnected between a VDD power line and an output node (terminal) of the gate, and one or more n-channel MOS field effect transistors(NFETs), located in an NMOS portion of the gate interconnected between a VSS power line and the output node of the gate. The PFETs and NFETs are interconnected in such a manner that whenever the input signals to the PFETs and NFETs are such that there is closed path from VDD through the PMOS portion to the output node, so that the voltage at the output node goes up to VDD (pulls up), there is then no closed path from the output node to VSS, so that there is no standby power dissipation. Similarly, there is no standby power dissipation when the voltage of the output node goes down (pulls down) to VSS as a result of a closed path being formed through the NMOS portion but not through the PMOS portion.
On the other hand, CMOS logic circuits suffers from signal skews caused by differences between pull-up and pull-down delays in CMOS logic gates more strongly than the faster bipolar ECL gates. This is a general problem when using slower gates in highly precise timing. Faster ECL gates make the skew invisible by virtue of the speed of switching, but slower CMOS gates cannot do so. These differences vary with variations in semiconductor manufacturing processing conditions, as well as with variations in operating power line voltages (VDD and VSS) and operating temperatures. Moreover, interconnecting wiring delays, caused by differences in relatively long lengths of the interconnecting wiring, also produce signal skews in CMOS multistage logic tree circuits. Therefore, it would be desirable to have a CMOS switching circuit arrangement which avoids all these signal skews.